The present disclosure relates to a phase comparison circuit to be used for a clock and data recovery circuit, and a data receiving unit using the phase comparison circuit.
In a field of recent information devices or digital devices, fast serial transmission is widely used to transmit large-volume digital data at high speed and low cost. A receiver for the fast serial transmission reproduces a clock in synchronization with a predeterminately encoded, received data array and reproduces data with a clock and data recovery circuit (hereinafter, abbreviated as “CDR”). One of the components of CDR includes a phase comparison circuit.
Japanese Unexamined Patent Application Publication No. 2002-314387 discloses a phase comparison circuit that accurately outputs a phase difference between a data input signal DI and a clock input signal CI as a difference in pulse width between an UP signal and a DOWN signal.